The Bus Design of Computer Organization Principle

Article source cxuan’s own public number: Computer Composition Principle Bus Design

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We know that a computer is composed of five major components: arithmetic unit, memory, controller, input device and output device , this concept is relatively abstract, in simple terms, the CPU contains arithmetic units and controllers, and memory also refers to It is the memory, and the input and output devices refer to the keyboard and the monitor respectively. These components of the computer need to work together to complete information processing. Then, how to communicate between these major components? on the 160b5a2bc05900 system bus , which is also the focus of our discussion in this article.

Know the bus

bus is a channel that connects two computers or multiple functional units together and allows them to exchange data with each other. The bus can also connect the computer and external devices together. The bus is a very important part of the computer system. On the need to know the following concepts.

• Bus width: The number of parallel data channels is generally used to define the width of the bus. The width of the general bus is 8-bit, 16-bit, 32-bit, and 64-bit. The most commonly used one is a 64-bit bus, a 64-bit wide bus at a time. Able to transmit 64 bits or 8 bytes of information.
• Bandwidth: Bandwidth is a measure of the data transfer rate on the bus. Increasing the number of parallel channels while keeping the data transmission rate constant can increase the bandwidth of the bus.
• Delay: Delay is the time interval from the sending of a data transmission request to the actual data transmission.

Bus classification

Below we mainly introduce two kinds of buses, one is chip bus , the other is system bus , on-chip bus generally refers to the internal CPU chip, between registers and registers, between registers and arithmetic unit ALU connection.

The system bus mainly refers to the information transmission medium of major components such as CPU and memory, memory and IO devices, CPU and IO devices. The system bus is mainly divided into the following three categories according to the difference of transmission information.

• Address line
• Data line
• Control line

Let’s take a closer look at these three types of buses.

Address bus

The address bus is mainly used to transfer the address of source data or destination data in the main memory unit.

The CPU uses the address bus to specify the location of the storage unit. How much information can be transmitted on the address bus, the CPU can address how many storage units.

In the above figure, the exchange of information between the CPU and the memory has passed through 10 address buses, and the data that can be transferred by each line is 0 or 1, so the data transferred by the CPU and the memory in the above figure is 2 to the tenth power.

Therefore, if the CPU has N address buses, then the width of this address bus can be said to be N. In this way, the CPU can look for 2 to the Nth power of memory units.

Data Bus

The data line, as its name implies, is the number of bits of data transferred at a time, and the number of bits of the data bus is the data bus width.

The data transfer between CPU and memory or other components is completed data bus. The width of the data bus determines the data transmission speed between the CPU and the outside world. Eight data buses can transmit one 8-bit binary data (that is, one byte) at a time. 16 data buses can transmit two bytes at a time, and 32 data buses can transmit four bytes at a time. . . . . .

Control bus

The control bus is a transmission line that sends out control signals on the bus. Common control signals are: clock (synchronous operation), reset (initialization operation), interrupt request/response, memory read and write, IO read and write, etc.

The control between the CPU and other components is accomplished through the control bus. How many control buses there are, it means how many kinds of control the CPU provides to external devices. Therefore, the width of the control bus determines the CPU's ability to control external components.

Computer-based connection

In the early stage of the Internet, most buses used scattered connections (there is also a bus connection, which will be described later). This connection method is shown in the figure below.

As you can see from the figure, the arithmetic unit is the core part of this distributed connection. This connection method will cause problems. When your CPU is busy calculating, the information exchange between IO and memory occurs. At this time, your arithmetic unit That is, the CPU has to stop, which leads to the interruption of the operation of the arithmetic unit, which seriously affects the work efficiency of the CPU.

You think, when you are writing an article, your target asks you: Why are you ignoring me today? So you have to let go of work and chat with her; when you deal with her emotions and continue to write an article for 5 minutes, then your readers have published a long comment to ask you questions. At this time, you can't help but reply. Sometimes you have to put aside writing articles, and then help him solve the problem. This shows that your writing efficiency will be high? The same goes for the CPU.

Of course, you can also choose to enter the focus mode without replying, which depends on the priority of the matter, and the CPU is the same.

Bus design

Memory-based connection

Later, in order to improve this situation, memory appeared. This structure is as follows

It can be seen that this connection method takes memory as the core, and the main functions of the components involved in the figure are as follows

• The input device converts commonly used information into a data form that the machine can recognize, such as keyboard and mouse, etc.
• Memory is used to store instructions and data
• The arithmetic unit is used to complete arithmetic and logical operations, and temporarily store the result of the operation in the arithmetic unit
• The controller is used to complete the command and control program and data input, operation and processing calculation results
• The conversion process of the output device is the reverse process of the input device, that is, the result of the operation is converted into a form that people can understand

Due to the close relationship between the arithmetic unit and the controller in the circuit structure, the arithmetic unit and the controller are usually collectively referred to as CPU , and the input/output devices are collectively referred to as IO devices, and the memory is memory.

Therefore, the composition of a modern computer is generally CPU + memory + input/output device .

After using this connection method, the information exchange between the IO and the main memory can not go through the arithmetic unit, and with the development and maturity of interrupt and DMA technology, the CPU efficiency has been greatly improved.

But this way, you can not solve flexibility connection between IO devices and hosts , because when we want to add a IO device, this connection can not handle, which put the bus connection.

Dual bus connection based on CPU

The bus uses a shared connection mode of multiple IO components. The bus is actually composed of many transmission lines, each of which can transmit binary data bit by bit. For example, 16 transmission lines can simultaneously transmit 16-bit binary codes.

The following is a CPU-centric dual bus structure

The connection method shown in the figure above is a kind of bus connection method, which connects various components to a set of common transmission lines. From the figure, you can understand dual bus: one group of buses connects the CPU and the memory, called the storage bus; the other group is used to establish a channel for exchanging information between the CPU and each I/O device, called the IO bus .

There are also problems with this connection method. When multiple components are connected to the bus, if two or more components send messages at the same time, signal conflicts will inevitably occur, resulting in invalid transmission. Therefore, only one component is allowed to send a message at the same time, but multiple components can receive messages.

Single bus structure design

If the CPU, main memory, and IO devices are all hung on a set of buses through the IO interface, a single-bus connection is formed.

Here is a question. What do you think is the biggest difference between the single-bus connection and the CPU-based dual-bus connection?

In the CPU-based dual-bus connection mode, the interaction between the CPU and the IO bus requires the participation of the CPU, and the interaction between the CPU and the memory also requires the participation of the CPU, so the CPU is doing work all the time, which is also attributable to the CPU. dead.

Single-bus connection connection mode, because the CPU, memory and IO are all hung on the same bus, the interaction between memory and IO does not require the participation of the CPU. This is the biggest change. There are also problems with this connection method, because there is only one set of buses, and conflicts will occur when all components need to exchange information. Therefore, in this design, it is necessary to set the priority of bus occupancy so that each component can follow Priority order to occupy the bus in turn. This is the real reason why locks are used as thread safety in programming languages.

Another problem is that the CPU does not directly interact with the memory, which greatly affects work efficiency.

Memory-centric dual bus structure

Another connection method is a dual-bus structure centered on the memory, and its design is as follows

This kind of bus design structure is very comfortable. It is based on the above single bus structure, adding a storage bus between the CPU and the memory. When the IO uses the system bus at a high frequency, the CPU and the memory can interact through the storage bus, which greatly speeds up the system work Efficiency, and reduces the bus overhead. It also retains the feature that it does not need to go through the CPU when interacting with memory and IO.

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