Diode implementation of OR gate and understanding of AND gate

Looking for some information, the diodes 与门 and 或门 seem to be simple, but to implement, the OR gate is easy to understand, and the most simple to implement, but for the AND gate, it is not to be realized. It's as I thought.

The premise of realizing an AND gate or an OR gate is to use the clamping function of the diode. The clamping function of the diode is to put it bluntly. In a parallel circuit, the voltage on the parallel circuit will be forced to be stepped down to the voltage of the diode. For silicon diodes, the voltage shared by the diodes in the circuit is about 0.7V. If a diode is connected in parallel in a parallel 5V circuit, then the voltage in this parallel circuit is all 0.7V, which seems counterintuitive. It stands to reason that in this 5V parallel circuit, the voltages at both ends should be 5V.

The upper part of this figure is a circuit of an OR gate. After the two switches are connected, the circuit of 800Ω in parallel is clamped to 0.7V, so the 200Ω resistor is a high voltage. In fact, here, in fact, I think it doesn't matter if this diode is needed. If not, it is equivalent to a short circuit for 800 ohms, and there is no voltage.

For the AND gate circuit below, the general circuit diagram gives the 200Ω resistance part and the diode part, which seems difficult to understand, and when you perform welding and testing by yourself, it is useless to weld according to this circuit diagram. The most fundamental The reason is that the meaning of the low level and the high level on the left side of the diode is not clearly understood. My first understanding was that the grounding part in the middle was missing, that is to say, I thought that the diode was naturally low level if it was not connected, and then directly connected to the high level, then the diode would not conduct, in fact Without this ground part, when the high level is not connected, the diode does not conduct at all. Naturally, there is no clamping effect.

Therefore, the so-called low level and high level of the input part of the AND gate circuit are equivalent to either connecting the negative pole or the positive pole, there is no open circuit, and the OR gate is only disconnected and not disconnected. Understanding AND gates in terms of OR gates makes it very difficult to understand.

For the AND gate, any one of the left is connected to a high level, and the other is connected to a negative electrode. From the figure, this diode forms a parallel circuit with the 1kΩ resistor on the right, and then the 1k resistor is clamped to a low level of 0.7V. And once the left side of the two diodes are high level, or disconnected, then naturally the clamping effect will not be achieved, and the 1kΩ resistor will naturally be high level. Generally, there are two incomprehensible points in the circuit diagram seen on the Internet. First, the 200Ω resistor here is generally given a high value on the circuit diagram. In fact, this resistance should be smaller than the output resistance. The main function of this resistance is to prevent When the two diodes are grounded, the entire circuit forms a short circuit. This diode is mainly used to limit current and prevent short circuits. The other is why the high level of the output terminal is not represented by the disconnected state of the two switches. I think the main reason here is because the AND gate is two high levels to get a high level. If it is represented by disconnection, then it is Indicates no signal.