Raph Levien, June 6, 2025: A follow-up to a blog post on Rust and SIMD programming. Presents a plan with goals like making SIMD programming ergonomic and safe, having a lightweight dependency, and supporting fine-grained levels.

• Goals: Similar to Highway, aiming for speedups in various workloads. Explicitly added goals include a lightweight dependency with no expensive transitive deps and support for at least SSE 4.2.
• Summary: Builds on fearless_simd#2 with code generation instead of manual curation. Supports a full cartesian product of SIMD widths and types. Considers explicit vs variable width, with 256 bits a sweet spot. Concerned about compile times and uses codegen to help.
• Explicit vs variable width: The design favors portable explicit width programming. 256 bits is good for most x86_64 and Neon chips. 512 bit chips are double-pumped and not significantly faster. For simpler workloads, add pulp-like types and operations.
• Light use of macros: Concerned about compile times. Macro expansion takes a large portion of time. Using codegen before publish may help, and simd_dispatch will remain a declarative macro.
• Topics discussed in the blog: Dispatch is done by runtime detection. Supports downcasting and has ergonomic features like core::ops support.
• Alternatives considered: Prototyped a DSL using proc macro infrastructure but found it costly and showed seams. Considered evolving pulp but it could be disruptive.
• On RVV and SVE: Marginal but becoming more important. Challenges include Rust support for intrinsics. Two modes for "scalable vector" SIMD.
• Considerations for WASM SIMD: WASM doesn't have runtime feature detection. SIMD capabilities are determined at compile time, and the Level enum compiles to nothing.
• Very small SIMD: In the embedded world, there are small SIMD extensions. Consider it an open question for now.
• Discussion: There are discussion threads on Linebender Zulip and Rust Zulip. The library is not yet usable for broad applications, but feedback is welcome.