逆向工程 386 处理器的预取队列电路

发布于 8 月 3 日

1985 Intel 386 Processor: Introduced the first 32-bit processor in x86 architecture with a 16-byte instruction prefetch queue to improve performance by fetching instructions from memory before needed.
- Prefetch Queue Circuitry:
  - Incrementer: Adds 1 to a pointer to step through memory using a faster approach like the Manchester carry chain and carry skip techniques to handle high-speed incrementing.
  - Alignment Network: Rotates data to align 32-bit values split across two rows of the prefetch queue for proper processing.
  - Sign Extension: Converts signed 8-bit or 16-bit values to 32 bits as needed for instructions.
- Limit Check: Stops prefetching when the fetch pointer reaches the limit of the Code Segment to avoid going outside the valid memory range using dynamic logic and XOR gates.
Instruction Flow: Instructions follow a tortuous path. The Bus Interface Unit reads instructions from memory and sends them to the prefetch unit. The prefetch unit stores them in the 16-byte queue and provides opcodes to the decoder one byte at a time. Data bytes go to the ALU through a 32-bit data bus.
Conclusions: The 386's prefetch queue contains about 7400 transistors, showing the rapid advance in processor technology. The prefetcher's complexity is due to backward compatibility and unaligned memory accesses.
Footnotes and References: Various details about the circuitry, including width changes, comparisons with other processors, clocking, and mnemonics for sign extension are provided. References to related articles and papers are also included.

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